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HD74ALVCH16270
12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
ADE-205-137 (Z) Preliminary 1st. Edition May 1996 Description
The HD74ALVCH16270 is used in applications where data must be transferred from a narrow high speed bus to a wide lower frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low to high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A to B direction, a two stage pipeline is provided in the A to 1B path, with a single storage register in the A to 2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active low output enables (OEA, OEB). The control terminals are registered to synchronize the bus direction changes with CLK. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
* VCC = 2.3 V to 3.6 V * Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) * Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) * High output current 24 mA (@VCC = 3.0 V) * Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16270
Function Table
Inputs CLK OEA H H L L OEB H L H L Outputs A Z Z Active Active 1B, 2B Z Active Z Active
Output enable
Inputs CLKENA1 L L L L H H H CLKENA2 H H L L L L H CLK X A L H L H L H X
Outputs 1B L
*2
2B 2B0 2B0 L H
*1 *1 *1 *1 *1
H *2 L *2 H
*2
1B0 1B0 1B0
L H 2B0
*1
A-to-B storage (OEB = L)
Inputs CLKEN1B H X L L X X CLKEN2B X H X X L L CLK X X SEL H L H H L L 1B X X L H X X 2B X X X X L H
Output A
A0 A0 L H L H
*1 *1
B-to-A storage (OEA = L)
H : High level L : Low level X : Immaterial Z : High impedance : Low to high transition Notes: 1. Output level before the indicated steady state input conditions were established. 2. Two CLK edges are needed to propagate data.
HD74ALVCH16270
Pin Arrangement
OEA 1 CLKEN1B 2 2B3 3 GND 4 2B2 5 2B1 6 VCC 7 A1 8 A2 9 A3 10 GND 11 A4 12 A5 13 A6 14 A7 15 A8 16 A9 17 GND 18 A10 19 A11 20 A12 21 VCC 22 1B1 23 1B2 24 GND 25 1B3 26 CLKEN2B 27 SEL 28
56 OEB 55 CLKENA2 54 2B4 53 GND 52 2B5 51 2B6 50 VCC 49 2B7 48 2B8 47 2B9 46 GND 45 2B10 44 2B11 43 2B12 42 1B12 41 1B11 40 1B10 39 GND 38 1B9 37 1B8 36 1B7 35 VCC 34 1B6 33 1B5 32 GND 31 1B4 30 CLKENA1 29 CLK
(Top view)
HD74ALVCH16270
Absolute Maximum Ratings
Item Supply voltage Input voltage
*1, 2
Symbol VCC VI
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VCC +0.5
Unit V V
Conditions
Except I/O ports I/O ports
Output voltage
*1, 2
VO I IK I OK IO
-0.5 to VCC +0.5 -50 50 50 100
V mA mA mA VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
Input clamp current Output clamp current Continuous output current
Maximum power dissipation at Ta = 55C (in still air) *3 Storage temperature Notes:
PT Tstg
1 -65 to 150
W C
TSSOP
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage High level output current Symbol VCC VI VO I OH Min 2.3 0 0 -- -- -- Low level output current I OL -- -- -- Input transition rise or fall rate Operating temperature t / v Ta 0 -40 Max 3.6 VCC VCC -12 -12 -24 12 12 24 10 85 ns / V C mA Unit V V V mA VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
HD74ALVCH16270
Logic Diagram
CLK CLKEN1B CLKEN2B CLKENA1 CLKENA2 OEB SEL OEA
29 2 27 30 55
C1
56 28 1
1D
1D C1 G1 1 1 CE C1 1D
CE C1 1D CE C1 1D CE C1 1D CE C1 1D
1 of 12 Channels
23
1B1
A1
8
6
2B1
HD74ALVCH16270
Electrical Characteristics (Ta = -40 to 85C)
Item Input voltage Symbol VCC (V) *1 VIH 2.3 to 2.7 2.7 to 3.6 VIL 2.3 to 2.7 2.7 to 3.6 Output voltage VOH Min 1.7 2.0 -- -- Max -- -- 0.7 0.8 -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 5 -- -- -- -- 500 10 40 750 A A A A V I OH = -100 A I OH = -6 mA, VIH = 1.7 V I OH = -12 mA, VIH = 1.7 V I OH = -12 mA, VIH = 2.0 V I OH = -12 mA, VIH = 2.0 V I OH = -24 mA, VIH = 2.0 V I OL = 100 A I OL = 6 mA, VIL = 0.7 V I OL = 12 mA, VIL = 0.7 V I OL = 12 mA, VIL = 0.8 V I OL = 24 mA, VIL = 0.8 V VIN = VCC or GND VIN = 0.7 V VIN = 1.7 V VIN = 0.8 V VIN = 2.0 V VIN = 0 to 3.6 V VOUT = VCC or GND VIN = VCC or GND VIN = one input at (VCC-0.6) V, other inputs at V CC or GND Unit V Test Conditions
Min to Max VCC-0.2 2.3 2.3 2.7 3.0 3.0 2.0 1.7 2.2 2.4 2.0
VOL
Min to Max -- 2.3 2.3 2.7 3.0 -- -- -- -- -- 45 -45 75 -75 -- -- -- --
Input current
I IN I IN (hold)
3.6 2.3 2.3 3.0 3.0 3.6
Off state output current
*2
I OZ I CC
3.6 3.6 3.0 to 3.6
Quiescent supply current I CC
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. For I/O ports, the parameter I OZ includes the input leakage current.
HD74ALVCH16270
Switching Characteristics (Ta = -40 to 85C)
Item Symbol VCC (V) 2.50.2 2.7 3.30.3 Propagation delay time t PLH t PHL 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Output enable time t ZH t ZL 2.50.2 2.7 3.30.3 Output disable time t HZ t LZ 2.50.2 2.7 3.30.3 Input capacitance Output capacitance CIN CIN / O 3.3 3.3 Min 150 150 150 2.0 -- 1.1 1.7 -- 1.0 1.9 -- 1.0 1.6 -- 1.0 2.6 -- 1.1 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.5 9.0 Max -- -- -- 6.5 5.8 5.1 6.0 5.4 4.7 6.8 6.4 5.5 7.5 6.8 6.0 7.4 6.5 5.8 -- -- pF pF Control inputs A or B ports ns CLK A or B ns CLK A or B SEL A CLK A ns CLK B Unit MHz FROM (Input) TO (Output)
Maximum clock frequency f max
HD74ALVCH16270
Item Setup time Symbol t su VCC (V) 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Hold time th 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Pulse width tw 2.50.2 2.7 3.30.3 Min 4.1 3.8 3.1 0.9 1.2 0.9 3.5 3.2 2.7 3.4 3.0 2.6 4.4 3.9 3.2 0 0 0.2 1.4 1.0 1.7 0 0.1 0.3 0 0 0.6 0 0 0.1 3.3 3.3 3.3 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns CLK "H" or "L" OE after CLK CLKEN1B or CLKEN2B after CLK CLKENA1 or CLKENA2 after CLK B data after CLK ns A data after CLK OE before CLK CLKEN1B or CLKEN2B before CLK CLKENA1 or CLKENA2 before CLK B data before CLK Unit ns FROM (Input) A data before CLK
HD74ALVCH16270
* Test Circuit
See under table 500 S1 OPEN
*1
GND 500
C L = 50 pF
Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ
Vcc=2.50.2V Vcc=2.7V, 3.30.3V
OPEN GND 4.6 V
OPEN GND 6.0 V
Note: 1. C L includes probe and jig capacitance.
HD74ALVCH16270
* Waveforms - 1
tr 90 % Input 10 % t PLH Vref 90 % Vref 10 % t PHL tf VIH GND
VOH Output Vref Vref VOL
* Waveforms - 2
tr 90 % Vref 10 % tsu th VIH GND VIH
Timing Input
Data Input
Vref
Vref GND tw VIH
Input
Vref
Vref GND
HD74ALVCH16270
* Waveforms - 3
90 % Vref 10 % t ZL Vref t ZH Waveform - B Vref t HZ VOH - 0.3 V 10 % t LZ tf tr 90 % Vref GND VOH1 Waveform - A VOL + 0.3 V VOL VOH VOL1 TEST VIH Vref VOH1 VOL1
Vcc=2.50.2V Vcc=2.7V, 3.30.3V
VIH
Output Control
2.3 V 1.2 V 2.3 V GND
2.7 V 1.5 V 3.0 V GND
Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , tr 2.5 ns, tf 2.5 ns. 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement.
HD74ALVCH16270
Package Dimensions
Unit : mm
14.00 -0.1 56
+0.3
29 6.10 +0.3 -0.1
1 0.20 +0.1 -0.05
0.50 28 0.08 M 8.10 0.3 10 Max 0.05 0.05 1.2 Max 0.15 0.05
0.40 Max
0.10
0.50 0.1 Hitachi code EIAJ code JEDEC code TTP-56D -- --
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

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